This invention relates to a method of producing a thin film transistor (TFT) array.
Thin film transistors are known to be field effect transistors in which the conductivity of the semiconductor fabricated between the source electrode and the drain electrode is controlled by a voltage applied to the third electrode (gate electrode) formed on the gate insulator in contact with the semiconductor.
The thin film transistor has been studied for its application to image sensors or display panels because of the ease of fabricating a switching array over a large area at a low material cost. For example, a display panel having a thin film transistor at each picture element can be greatly improved in its performance. There are, at present, a lot of display media devices such as gas plasma, electroluminescence, fluorescent displays activated by a low voltage electron beam, liquid crystal, electrochromic, electrophoretic and so on. In order to have an excellent contrast on the matrix display panel utilizing these display media devices, it is essential that the display medium have a sharp threshold in the voltage-brightness characteristics. However, some of the display media described above lack this sharpness in the threshold and are not suitable for a matrix display with many picture elements. Furthermore, even the matrix display panel with sharp threshold characteristics suffers from the decrease in brightness or response speed due to the decrease in the duty ratio for activation as the picture elements increase. A thin film transistor switching element, and, if necessary, a storage capacitor at each picture element, thus serve to improve the contrast ratio, the brightness and the response speed in the matrix display panel with a large number of picture elements.
Conventional methods of producing thin film transistor arrays are reviewed, for example, in Physics of Thin Films, Vol. 2, pp. 147-190, 1964, by P. K. Weimer, Academy Press, and Proceedings of the Society for Information Display, Vol. 17, pp. 39-55, 1976, by T. B. Brody. In these conventional methods, electrodes, semiconductors and gate insulators with desired patterns are formed on an insulating substrate by vacuum deposition through a metal mask with a desired aperture in contact with the surface of the substrate. The conventional method in which materials forming the electrodes, semiconductors and gate insulators are successively deposited on each other under high vacuum by one pumpdown has advantages in that a clean layer without contamination can be obtained using fewer production steps. However, it has some disadvantages in that it is difficult to obtain an evaporation metal mask with high precision and no defects, and in that high cost equipment is necessary for the successive exchanges of metal masks or the precise adjustment of the relative position of the two metal masks.
Furthermore, a thin metal mask is essential for the fabrication of a thin film transistor array of high density, and it becomes more difficult to accomplish a uniform contact between a thin metal mask and the substrate due to a decrease in a mechanical strength of the metal mask.
Thus, in the conventional methods, integration density of the array and the precision in dimension and position of the fabricated thin film transistor are seriously incompatible to each other.
A further disadvantage in the conventional method is the problem in the mis-registration of deposited layers caused by the difference between the thermal expansion coefficients of the substrate and the metal mask. The thermal expansion coefficients of glass substrates per degree centigrade are between about 3.times.10.sup.-6 (Pyrex glass) and about 9.times.10.sup.-6 (soda glass). On the other hand, those of metal masks are, e.g., (1 to 2).times.10.sup.-6 (invar), 6.times.10.sup.-6 (kovar), 16.4.times.10.sup.-6 (stainless steel: 18Cr, 8Ni). The difference of 1.times.10.sup.-6 /.degree.C. in the thermal expansion coefficient between the substrate and the metal mask results in a misregistration of about 23 .mu.m under the temperature of 250.degree. C. in a dimension which is 100 mm at room temperature.
It is quite difficult to select a combination of the substrate and the metal mask with a difference in their thermal expansion coefficients less than 1.times.10.sup.-6 /.degree.C., and at the same time the mis-registration of about 23 .mu.m is an unacceptable amount. As described above, it is hopeless to fabricate, by the conventional method based on the use of metal masks, an array of large size with an integration density more than about 50 elements/inch.
A method of fabricating a thin film transistor array without using a metal mask is described, for example, in Proceedings of the SID, Vol. 14, No. 4, 1973 or in Philips Technical Review, Vol. 27, 1966.
According to these conventional methods, electrodes of source, drain or gate are formed by photolithography method. The thin film transistor according to the former one of the above-noted conventional methods has, as shown in FIG. 1, features a structure wherein a gate insulating layer 1 and semiconducting layer 2 are deposited almost uniformly on the surface of the substrate 3, without being patterned. On the other hand, the latter one of the above-noted conventional methods discloses the TFT structure as shown in FIG. 2 in which electrodes of source, drain and gate, 4, 5, 6, respectively, are formed on the same surface of the substrate 3, and a gate insulator 1 which is formed by an anodic oxidation method covers only the gate electrode 6.
The present inventors have tried these conventional methods based on the use of metal masks or photolithography techniques in order to fabricate a TFT array with a high density, and have found that the metal mask method surfaces from a great difficulty when used for the purpose of fabricating a TFT array of high density, as already described before. On the other hand, as apparent from FIGS. 1 and 2, those TFT's have the same feature that the semiconducting layer 2 is formed on the upper surface of the insulating layer 1 when viewed from the side of the substrate 3.
The display panel combined with the TFT array usually uses, as display medium, an electroluminescence layer, a liquid crystal layer or a electrophoretic suspension layer. Such a display medium is usually sandwiched between the surface of the substrate with the TFT array and the common electrode. Therefore, the display medium is directly in contact with the surface of the semiconducting layer of the TFT. In order to avoid the deterioration in the characteristics of the display medium and/or the TFT's due to the electrochemical interaction between them, the semiconducting layer must be protected by an inert insulating layer. Since the protection layer must not cover the drain electrode which is electrically connected to the display medium, the step of depositing an inert protection layer with a specific pattern becomes inevitable. Furthermore, the disadvantage in the structure as shown in FIG. 1 lies in that the semiconducting layer 2 is apt to deteriorate in its characteristics due to the direct contact with the solvent when etching the semiconducting layer into a desired pattern, and furthermore, the dissolving peeling or contamination of the semiconducting layer often arises.
The TFT structure as shown in FIG. 2 has a disadvantage that it is necessary to remove the portions 2', as shown in FIG. 2, of the semiconducting layer, for example, by a photoetching technique in order to expose the given surface of the source and drain electrode if the TFT's produced are intended for use as a display panel. Due to this photoetching step, the TFT's, suffering from the peeling or contamination of the semiconducting layer, cannot show stable and reliable performance.
The conventional methods for fabricating the TFT based on the photolithography method are not always aimed at the application of the TFT array to display devices and are those that are not directly applicable to this purpose.
The reason why the photolithography method most popularly adopted in silicon IC technology has not yet yielded a satisfactory solution in the fabrication of the TFT's seems to be due mainly to the fact that that in addition to the difficulty in the precise photoetching of large size devices, the contamination during the etching process and the complexity of the processes, a practical production method has not yet been developed both in materials and processes.